`include "defines.v"
module ctrl(
	input wire rst,
	input wire pause_from_id,
	input wire pause_from_ex,
	output reg[5:0] pause
);
	//PAUSE[5:0]分别对应pc,取指，译码，执行，访存，写回阶段是否暂停
	always@(*)
		if(rst == `RstEnable)
			pause = 6'b000000;
		else if(pause_from_ex == `PAUSE)
			pause = 6'b001111;
		else if(pause_from_id == `PAUSE)
			pause = 6'b000111;
		else
			pause = 6'b000000;
endmodule
